Memory cells in non-volatile memory devices typically store data by holding respective analog values representing the data. Memory cells programmed with certain data are typically erased before being rewritten with other data. Various methods for erasing and programming non-volatile memory cells are known in the art. For example, U.S. Pat. No. 8,787,094, whose disclosure is incorporated herein by reference, describes an erase operation for a 3D stacked memory device that selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, faster-erasing memory cells are less likely to be over-erased. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of the subset. An inhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
U.S. Patent Application Publication 2014/0098615, whose disclosure is incorporated herein by reference, describes a method for detecting latent slow erase bits in a non-volatile memory (NVM). At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.
U.S. Patent Application Publication 2014/0082460, whose disclosure is incorporated herein by reference, describes dynamic control of a program-erase window in a NAND memory device. In one embodiment, the program-erase window is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage in subsequent program/erase cycles over the life time of the NAND memory device based on the current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher program verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages in subsequent program/erase cycles based on the current cycle count value.